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Revised October 2007

DDR memory module M-10 (Stratix II version)
Memory module in which a DDR SDRAM with a 400MHz memory clock can be mounted
A maximum of 1GB (512MB x 2) of SO-DIMM type DDR SDRAM memory can be mounted.
Ideal for development of applications for image and video containing large scale FPGA and requiring large amounts of memory.

- Memory module: two 200-pin SO-DIMM DDR 200/400 MHz, mounted on the surface and the back side.
  Off-the-shelf PC3200 DDR memory module (for laptop PC) can be used. *1)
- FPGA: Altera Stratix II FPGA (EP2S130FF1508) *2)
- Up to 8 functional modules can be mounted on B-1 Base System.
- Total 730 user I/Os (excluding DDR memory module interface).
- Altera configuration cable supports; Byte Blaster II, Byte Blaster MV, USB-Blaster and Master Blaster serial/USB Communication Cable
Altera configuration cable
- Design Gateway configuration supports: FlashLink and JtagLink

DDR photograph

Function block diagram    

· CN 1-4 for connecting to the base system and I/O for connecting to CN5 for connecting to multi-purpose I/O can all be used by the user.
CN 1/4 include 175 multi-purpose I/Os, and there are 2 each for dedicated clock input/output, to give a total of 179.
CN 2/3 include 176 multi-purpose I/Os, and there are 2 each for dedicated clock input/output, to give a total of 180.
CN 5 includes 12 multi-purpose I/Os. CN 1-4, 5 have a total of 718 I/Os.

· 2 OSCs can be mounted for each of DDR memory and the system clock. 3 SMA connectors can be mounted for external clock input.

· Clock input to modules include 2 each to CN 1-4, and the clock for DDR memory, to give a total of 9. These can be freely selected as input from the module base system, external input via OSC, SMA connectors on the module, or input from another module, etc.

· The 2 DDR memories mounted on the module and FPGA are connected by the data bus (DQ/DQS) as a common signal. Other addresses, blocks, and control lines are connected independently.

· All the inputs and outputs of the base system (PCI, LED, DIP-SW, ROT-SW, etc.) can be used.

· FPGA's I/O power supply voltage value can be changed by jumpers on the board. The standard configuration is 2.5 Volts.

DDR Function block diagram

Sample IP core    

PC 3200 (DDR-200/400 MHz) memory test circuit.*1) *3)
· I/O pin toggle load test circuit.


* 1) confirmed by using Altera MegaCore DDR & DDR2 SDRAM Controller. PC3200 is limited to use on only one side (either surface or back side).
2) EP2S180-F1508 may be available.
3) In the Read/Write test, operations to the front and rear sides are confirmed independently.

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