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Top page>>Product information>>Base board with FPGA mounted B-20 (Virtex-4 version)

Revised October 2007


Base board B-20 with FPGA mounted (Virtex-4 version)
New base board guaranteed for operation at 200MHz with Virtex-4 mounted in the FPGA.  Accverinos series functional modules can be mounted.Provided with USB 2.0, PC2700 DDR memory (maximum 1GB can be mounted), PCI, and other interfaces.  Also, by connecting several units it can be used as an even larger scale verification platform.
Features    
 

- DDR memory module: 200-pin SO-DIMM PC2700 (166/333 MHz), 512 MB, fast SRAM, 16 M-bits.
- On-board memory: PC2700 (166/333 MHz) DDR memory, 512 MB.
- FPGA: Xilinx Virtex-4 XCE4VLX100/160/200-FF1513.
- Interface: USB 2.0 and PCI.
- Accverinos series functional module can be mounted (Data transfer speed between B-20 and the functional module is assured up to 200 MHz).
- Maximum 2M ASIC gate count circuit (when using XCE4VLX200 and M-20 functional module).
- Flexible connectivity by using PCI board or custom interface board.
- Chain connectivity with multiple B-20 Base Systems.
- Gated-clock can be realized on B-20 Base System.
- Micro ATX Chassis (easy to use).
- Sample FPGA circuit core-IP (memory controller) and PC base software.
- Sample software (Windows driver and application software) supplied as source code.

B-20 image
>>Display expanded view
 
 

Function block diagram    
   

· UWSCSI connectors can be freely used by users.
· Accverinos functional modules can be mounted to CN1 - CN4.
· SRAM can be used as shared memory for the Accverinos function modules.
· Commercial PCI board can be connected to the PCI connectors.
· PCI-Express connectors can be used as user I/O.
· PLL provides unskewed CLK to Virtex-4, Virtex-II Pro, Accverinos functional modules .For each CLK system, gated clocks are available.

 
B-20 Function block diagram

Sample IP core    
   

· DDR memory controller
· High speed transmission circuit between FPGAs
· PLL control circuit

 
 

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